Modern semiconductor devices such as, for example, integrated circuit (IC) devices or chips may typically be manufactured by processing a semiconductor carrier such as a wafer. Integrated circuits may include a plurality of layers, e.g. one or more semiconducting, insulating, and/or conducting layers, which may be stacked one over the other. In this connection, overlay (alignment) of an upper layer to a lower layer may be important. Alignment marks may typically be used for alignment, for example when aligning lithographically defined layers e.g. by means of a stepper or scanner.
When adjusting litholayers using a stepper/scanner apparatus, alignment jumps may occur.
For obviating this problem, the stepper/scanner apparatus conventionally includes a software solution which checks if contrast differences at measurement positions (e.g. at measurement bars) are larger than between the measurement positions. Further, marks adjacent to the measurement bars (fence bars) are checked.
Disadvantages of the software solution are that the software solution may not work properly or may have to be deactivated, respectively, during the alignment process if interferences bring about high contrast differences between the measurement bars, if the width of the bars is equal to half the distance between the bars, or if the bars adjacent to the measurement bars (i.e. the fence bars) show a contrast difference which is different when compared to the measurement bars.
It may be desirable to provide an alternative way to determine and/or avoid alignment jumps, without using the software solution.